Congratulations to the entire UTD and Raytheon team for winning the 2025 GOMACtech best student poster award. Special thanks for Chailtai Sathe, first author, and Aric Fowler for presenting the paper entitled “What to Redact? Guidelines for Cost-Effective Hardware Intellectual Property Protection”, by Sathe, A. Fowler, C. Sechen, B. Carrion Schaefer, Y. Makris The University of Texas at Dallas, and M. Zaman and R. Narumi Raytheon, An RTX Business.
Best student poster award
I have released the second edition of High-Level Synthesis Made Easy.
The updated version includes revisions and additional material including a chapter with advanced HLS optimizations, and a chapter with examples.
A PDF copy is available at www.hlsbook.com and hard copy can be purchased on Amazon here.
The DARClab hosted at UT Dallas the 43rd IEEE International Conference on Computer Design ( ICCD 2025) between November 10-12. Great technical presentations, keynotes from Synopsys, NVIDIA and AMD, tutorials, LLM for hardware design challenge.
Congratulations to Chaitali (Dr. Sathe) for successfully defending her PhD entitled ” Evolving Defense Mechanisms and Attack Frameworks in Hardware IP Security”. Well done!
We won ACM GLSVLSI 2025 best poster award!
The DARClab will organize the 43rd IEEE International Conference on Computer Design (ICCD 2025) here at the University of Texas at Dallas from November 10th to 12th. You can find more information at www.iccd-conf.com
Today we announce the creation of highX Technologies, a spin-off the DARClab that builds upon the technology and expertise accumulated during the last 12 years at the lab. highX technologies is dedicated to making hardware design easier by providing Behavioral IPs written in ANSI C and SystemC optimized for High-Level Synthesis (HLS). The company also provides HLS and FPGA consulting and training courses. More information at highX services.
We won the best paper award at the 2022 ACM ACM Great Lakes Symposium on VLSI [GLSVLSI’22].
Md Imtiaz Rashid and B. Carrion Schafer, Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration
The paper basically covers how to quickly find the Pareto-optimal designs for a given ASIC technology, but using free FPGA HLS tools and then use machine learning to convert those results into ASIC equivalent.
